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Search - fifo vhdl code

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[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[MPI] v2_fifo_vhd_258

Description: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Platform: | Size: 92160 | Author: muerqing | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] fifoi

Description: 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
Platform: | Size: 2048 | Author: 云 | Hits:

[VHDL-FPGA-Verilog] gencontrol

Description: 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
Platform: | Size: 1024 | Author: ted yang | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

Description: 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
Platform: | Size: 918528 | Author: ningning | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[VHDL-FPGA-Verilog] vhdlfifo1

Description: fifo - source code for first in first out(fifo) using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] vhdlfifo

Description: fifo- source code for fifo using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[Software Engineering] source_code

Description: verilog code fifo memory usb
Platform: | Size: 4096 | Author: mohsen | Hits:

[VHDL-FPGA-Verilog] HighSpeedFIFOsInSpartan-IIFPGAs

Description: This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.
Platform: | Size: 30720 | Author: fjmwu | Hits:

[VHDL-FPGA-Verilog] xapp205_fifo_ctl

Description: XAPP205 Xilinx FIFO Controller VHDL code
Platform: | Size: 47104 | Author: jc | Hits:

[VHDL-FPGA-Verilog] FIFO24_psconv

Description: fifo buffer vhdl code
Platform: | Size: 1024 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] FIFO_ise11migration

Description: fifo buffer vhdl code
Platform: | Size: 23552 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] atapi_ctl_2_5

Description: fifo buffer vhdl code
Platform: | Size: 7168 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] atapi_ctl_2_6

Description: fifo buffer vhdl code
Platform: | Size: 7168 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] actel_FPGA_example_source

Description: actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
Platform: | Size: 4096 | Author: leo | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo in vhdl file code
Platform: | Size: 1024 | Author: motti | Hits:
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